This invention relates to automatic test systems, and more specifically to automatic test systems utilizing timing generators which provide timing signals to an electronic device or circuit being tested.
Automatic test systems are well known in the prior art. FIG. 1 shows a block diagram of a typical prior art automatic test system 10. Test system 10 includes master clock 11, vector sequencing logic 12, device under test (DUT) power supplies (13), parametric measuring unit (PMU) 14, central processing unit (CPU) 15, computer memory 16, local peripheral devices 17, communication interface 18, and user work stations 19. Master clock 11 is the master system clock and provides a master clock signal which is typically generated from a very stable element such as a quartz crystal. Vector sequencing logic 12 serves to sequentially access test vectors stored in vector memory 22 in order to test DUT 30. DUT power supplies 13 serve to, under CPU control, provide desired voltage and current levels to device under test (DUT) 30. PMU 14 serves to, under CPU control, measure selected electrical parameters of DUT 30. CPU 15 controls the overall operation of test system 10. Computer memory 16 serves as a means for storing data for use by CPU 15. Local peripherals 17 typically are peripherals such as line printers, video displays, and the like. Communication interface 18 may, if desired, be provided in order to allow test system 10 to communicate with other systems. User work stations 19 are provided in order to allow a user to control the operation of test system 10, such as in order to load specific test programs for testing desired devices, and for monitoring certain test results. Computer bus 20 serves to allow interconnection between CPU 15, computer memory 16, local peripheral 17, communication interface 18, user work stations 19, and additional computers or peripherals (not shown).
Test system 10 includes a limited number of timing generators 24 which each provide a single analog timing signal having its leading edge and trailing edge controlled by CPU 15 or associated hardware. In such prior art test systems, the number of timing generators was limited because timing generators are rather expensive, and in the early days of automatic test systems, the devices to be tested were relatively small and unsophisticated as compared with today's devices, and thus only a relatively few (i.e., approximately sixteen) timing generators were necessary in order to perform all the electrical testing of the device under test. In order to allow the timing signals provided by these limited number of timing generators to be used on any lead of the device under test, a rather complex switching matrix 25 is utilized in order to function essentially as a cross point switch to allow the signals from the limited number of timing generators to be applied to selected ones of wave formatters 26. This also allows a single timing signal to be applied to a plurality of leads of DUT 30 in a plurality of formats during a single testing period. As the number of leads on DUT 30 increases with increasing complexities in electronic devices, the switching matrix 25 must be made increasingly larger and complex, and thus becomes more and more expensive.
Wave formatters 26 serve to receive timing signals from the limited number of timing generators 24 and provide to pin electronics 27 the appropriate test waveform. Certain of these test waveforms are shown in FIG. 2a, although it is understood by those of ordinary skill in the art that other such test waveforms are possible. FIG. 2a shows a plurality of five periods of a timing generator, with a test data provided by vector memory 22 being a logical 0, 0, 1, 1, and logical 0, respectively, during these five timing periods. All transitions are reflected to one or more edges of the timing generators. The remaining portions of FIG. 2a show the result of combining the timing generator information and the test data information in order to provide a nonreturn to 0 - true data (NRZ) signal with the edges appearing at the beginning of each timing generator clock period, NRZ - false data with the edges appearing at the beginning of each timing generator clock period return to zero (RTZ) - true data, return to one (RTO) - false data, and RTZ - false data.
Test system 10 also includes vector memory 22. Vector memory 22 stores a plurality of test vectors which in essence each consist of a plurality of bits defining the binary signals to be applied to DUT 30, and the proper output signals which are to be received by a properly functioning device under test in response to the input signals defined by that test vector word. In practice, CPU 15 controls vector memory 22 in order to cause vector memory 22 to sequentially provide to tester data bus 23 a plurality of test vectors. These test vectors are received by wave formatters 26. Wave formatters 26, in response to the test vector supplied by vector memory 22 and the timing signals provided by the limited number of timing generators 24 as routed by switching matrix 25, provide analog signals to pin electronics 27 which in turn provide analog test signals to DUT 30.
Wave formatters 26 (FIG. 1) are controlled by CPU 15 via tester access bus 21 in order to select the appropriate test waveform for each lead of the device under test 30. Although only six such wave formatters are shown in FIG. 1, such prior art computerized test sytems contain a wave formatter for each lead of the device under test which is capable of being simultaneously tested. This is often on the order of 60 to 120 leads, and thus 60 to 120 wave formatters are provided. The output signals from wave formatters 26 are provided to an appropriate one of pin electronics 27. Here again, a plurality of pin electronics are provided, one such pin electronics circuit for each lead of the device under test which is capable of being simultaneously controlled by computer test system 10. Pin electronics 27 serves to combine the analog signals from wave formatters 26 and the voltages and currents provided by DUT supplies 13 to provide appropriate test signals to DUT 30.
In testing electronic devices, a number of factors are of importance. First of all, the ability to force selected voltages and currents with accuracy is essential. Secondly, the ability to measure current levels and voltage levels as a result of the testing operation, is important. Thirdly, accurate timing of the test signals applied to the device under test or measured from the device under test is essential. For example, in a typical memory device such as a RAM, a ROM, or a PROM, appropriate addressing signals are applied to the device under test, and the device under test provides an output word which is compared with a table of correct data which should be stored in the memory device. Naturally, all memory devices require a certain amount of access time, and thus the tester must wait for a certain period of time after applying address signals prior to reading the output word from the device under test to determine if the output word from the device under test is correct. As a first requirement, sufficient timing voltage and current resources must be available to exercise all the pins of the device under test for each test cycle. Unfortunately, as integrated circuit devices become more complex, the limited number of timing generators provided can become insufficient, requiring complex schemes to allow testing of all pins with the limited number of timing generators. Accordingly, test system 10 must be capable of very accurately providing timing information to a device under test and measuring the time when information is returned by the device under test.
Furthermore, manufacturers specify and customers demand that such electronic devices operate at certain speeds. In other words, for the example of memory device, it is expected that within a certain time after address signals are applied, the user can expect to receive appropriate data on the output leads of the memory device. Accordingly, it is essential when testing such a device that the output signals be received within a certain specific time after providing the address signals to the device under test. Accordingly, test system 10 must be capable of very accurately presenting timing information to a device under test and measuring the time when information is returned by the device under test. Therefore, it is essential that, once timing generators 24 provide their timing signals under the control of central processing unit 15 to vector memory 22, these timing signals arrive at the appropriate leads of DUT 30 as accurately as possible. Unfortunately, as in any system, there are propagation delays between timing generators 24 and DUT 30. Furthermore, these propagation delays differ, depending upon the exact path the timing signals must take from timing generators 24 to their appropriate leads of DUT 30. In other words, each wave formatter 26 has its own specific propagation delay. Secondly, each pin electronics 27 also has its own specific propagation delay. Thirdly, switching matrix 25 provides additional and unequal propagation delays to each timing signal being routed from timing generators 24 to wave formatters 26. In the case where a single timing signal is being routed to a plurality of wave formatters and thus leads of DUT 30, the timing signal will encounter different propagation delays on its route to the various leads of DUT 30. Each of the propagation delays provided by switching matrix 25, wave formatters 26, and pin electronics 27 are cumulative in nature, and thus each timing signal is delayed by a unique propagation delay when passing from timing generators 24 to DUT 30. Adjustments must be made in order to make each of these propagation delays as equal as possible in order to maintain the relative timing of the timing signals once they reach device under test 30. Accordingly, a number of so-called "deskewing" elements are provided in each path between timing generators 24 and DUT 30. Such deskewing elements 31 are shown by way of example in a selected path of switching matrix 25, a selected one of wave formatters 26, and a selected one of pin electronics 27, although it is understood that each path in switching matrix 25, each wave formatter 26, and each pin electronics 27 may have its own deskewing element 31 for maximum accuracy. Deskewing elements 31 serve to provide an additional and adjustable propagation delay such that the total propagation delay along each path from timing generators 24 to device under test 30 may be made to be equal. Manual or computer controlled deskewing elements may be used. Manual deskewing elements 31 typically comprise RC delay circuits and are generally manually adjusted. In other words, during manufacture of the computer test system 10 and during subsequent repair and preventive maintenance operations, a skilled technician is required to utilize expensive test equipment in order to measure the propagation delay between timing generators 24 and the leads of a device under test 30. These technicians must then take great care in order to manually adjust all or some of the deskewing elements 31 in order to cause the propagation delay between timing generators 24 and DUT 30 to be made as close as possible. Unfortunately, this is a rather time-consuming task which requires a skilled technician and expensive measurement equipment. Furthermore, it is often found that such adjustments must be made rather frequently in order to ensure that the propagation delays between timing generators 24 and device under test 30 remain within the required specification. In addition to being rather expensive, such readjustments necessarily cause computer test system 10 to be taken out of service, resulting in undesirable down time, and thus a loss of production capability of computerized test system 10. Also, as the complexity of the timing path grows, it becomes more difficult to make the propagation delays provided by all the paths equal. At the same time, customers are asking for increased accuracy to test faster, more complex devices. Newer deskewing elements use digital to analog converters which provide an analog value in response to a digital word which controls the switching threshold voltage level on a gate, thereby providing an adjustable gate propagation delay. This simplifies the technician's job, but the problem of having a complex signal path which requires deskewing, remains. Such deskewing elements are rather complex and costly, and not completely accurate.
In addition to the fact that the propagation delays between timing generators 24 and DUT 30 are different and must be adjusted, it has also been found that the propagation delays provided by wave formatters 26 vary depending upon whether the data provided by vector memory 22 which controls that wave formatter is a logical 1 or a logical 0. Because this type of skew in the propagation delay is dependent upon the test data, such data dependent skew has heretofore been either impossible, or incredibly difficult and only roughly approximate to deskew.
Accordingly, it is seen that the errors which occur in the timing signals provided to device under test 30 are caused by several sources;
1. The error in the centrally-generated timing signals provided by timing generators 24. These errors are due to the limits of the resolution of timing generators 24 and calibration error. PA1 2. Error in the switching matrix 25, due to drift and cross talk. PA1 3. Error in deskew elements 31, due to limitations of resolution, drift, and measurement errors made during adjustment of deskewing elements 31. PA1 4. Error in wave formatters 26. PA1 5. Variation in the rise time of signals at DUT 30 due to differences in the specified voltage swings at device under test 30. PA1 6. Error in master clock 11 due to drift, cross talk, and calibration errors. Having these multiple sources of error in a prior art system is a problem in itself. Since timing information is subject to each of these errors sequentially as it proceeds from timing generators 26 to DUT 30, standard statistical analysis dictates that the overall error is the sum of the individual error terms. Even when all elements of the timing path are built with the best available technology, the overall error will be the sum of these individual errors, and greater error is present than if fewer sources of error were present.
Another major problem with adjusting deskewing elements 31 contained within switching matrix 25 is that, during operation of test system 10, switching matrix 25 is constantly being reorganized in order to cause the timing generators 24 to be connected to various wave formatters 26. Due to this switching of matrix 25, the propagation paths and thus the propagation delays through switching matrix 25 are constantly changing. This means that deskewing elements 31 contained within switching matrix 25 can only be approximately adjusted to remove an average amount of deskew which will be provided by switching matrix 25. However, in practice, a selected path through switching matrix 25 will generally have either a greater or less propagation delay than this "average" propagation delay through switching matrix 25, and thus deskewing elements 31 contained within switching matrix 25 are capable of only approximately deskewing switching matrix 25.